1. Field of the Invention
This invention relates generally to the field of semiconductor device manufacturing and, more particularly, to a method and apparatus for method and apparatus for determining control actions incorporating defectivity effects.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the quality, reliability and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in a continual improvement in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing the defects in the manufacture of the components of a typical transistor also lowers the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
Generally, a set of processing steps is performed on a lot of wafers using a variety of process tools, including photolithography steppers, etch tools, deposition tools, polishing tools, rapid thermal process tools, implantation tools, etc. The technologies underlying semiconductor process tools have attracted increased attention over the last several years, resulting in substantial refinements. However, despite the advances made in this area, many of the process tools that are currently commercially available suffer certain deficiencies. In particular, such tools often lack advanced process data monitoring capabilities, such as the ability to provide historical parametric data in a user-friendly format, as well as event logging, real-time graphical display of both current processing parameters and the processing parameters of the entire run, and remote, i.e., local site and worldwide, monitoring. These deficiencies can engender non-optimal control of critical processing parameters, such as throughput, accuracy, stability and repeatability, processing temperatures, mechanical tool parameters, and the like. This variability manifests itself as within-run disparities, run-to-run disparities and tool-to-tool disparities that can propagate into deviations in product quality and performance, whereas an ideal monitoring and diagnostics system for such tools would provide a means of monitoring this variability, as well as providing means for optimizing control of critical parameters.
One technique for improving the operation of a semiconductor processing line includes using a factory wide control system to automatically control the operation of the various process tools. The manufacturing tools communicate with a manufacturing framework or a network of processing modules. Each manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface that facilitates communications between the manufacturing tool and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control script based upon a manufacturing model, which can be a software program that automatically retrieves the data needed to execute a manufacturing process. Often, semiconductor devices are staged through multiple manufacturing tools for multiple processes, generating data relating to the quality of the processed semiconductor devices.
During the fabrication process various events may take place that affect the performance of the devices being fabricated. That is, variations in the fabrication process steps result in device performance variations. Factors, such as feature critical dimensions, doping levels, contact resistance, particle contamination, etc., all may potentially affect the end performance of the device. Various tools in the processing line are controlled in accordance with performance models to reduce processing variation. Commonly controlled tools include photolithography steppers, polishing tools, etching tools, and deposition tools. Pre-processing and/or post-processing metrology data is supplied to process controllers for the tools. Operating recipe parameters, such as processing time, are calculated by the process controllers based on the performance model and the metrology information to attempt to achieve post-processing results as close to a target value as possible. Reducing variation in this manner leads to increased throughput, reduced cost, higher device performance, etc., all of which equate to increased profitability.
Target values for the various processes performed are generally based on design values for the devices being fabricated. For example, a particular process layer may have a target thickness. Operating recipes for deposition tools and/or polishing tools may be automatically controlled to reduce variation about the target thickness. In another example, the critical dimensions of a transistor gate electrode may have an associated target value. The operating recipes of photolithography tools and/or etch tools may be automatically controlled to achieve the target critical dimensions.
In some cases, the goal to achieve target values may competes with the simultaneous goal of minimizing defects in the fabricated devices. Defects can take the form of particle contamination, missing or extra patterns, electrical defects, feature damage (e.g., from overpolishing), electrical faults, etc. Different processes performed during the fabrication of devices, by nature, have different propensities for inducing defects in the processed devices. A process control variable that is modified to achieve a target value goal may also effect the propensity of the process to induce defects. For example, in a chemical mechanical planarization process, process variables, such as polishing pressure, polish time, polishing rotation speed, etc. may be controlled automatically to achieve desired process layer removal rates and/or wafer surface uniformity characteristics. However, changing the process control variables also has the effect of changing the defectivity characteristics of the process. For example, as polishing pressure or time increases, the likelihood of damaging the features underlying the polished layer increases. If an underpolishing condition exists, remnants of the process layer may be still present in undesirable locations.
FIG. 1A illustrates a cross-section of an exemplary semiconductor device 100 that is subjected to a planarization process. Process variables associated with the planarization process may be controlled to achieve desired post-planarization targets. The semiconductor device 100 includes a base layer 110 with a plurality of trenches 120 defined therein. For example, the base layer 110 may be a dielectric layer (e.g., dielectric constant less than 5.0), such as silicon dioxide, and the trenches 120 may be used to form copper interconnect lines. In another example, the base layer 110 may be a substrate layer (e.g., an epitaxial silicon layer formed over a bulk silicon substrate), and the trenches 120 may be used to form shallow trench isolation (STI) structures between active regions of subsequently formed devices (e.g., transistors). A process layer 130 (e.g., copper for an interconnect line and silicon dioxide for an STI structure) is formed over the base layer to fill the trenches 120. One or more intermediate layers, such as a stop layer (not shown) may be formed between the base layer 110 and the process layer 130.
As seen in FIG. 1B, the process layer 130 is polished to remove the portions not disposed within the trenches 120. Various endpoint techniques may be used for determining the end point for the polishing process, however, these endpoint detection techniques are approximate, and some polishing may continue after the process layer 130 has been cleared.
The chemical slurry used in the polishing process typically has a higher etch rate for the material of the process layer 130. Hence, as the polishing process nears completion, the process layer 130 will be removed at a faster relative rate than the base layer 110 or underlying stop layer (not shown). A flexible polishing pad used in the polishing process may conform to the surface of the base layer 110 and process layer 130 and continue to polish the process layer 130 at a faster rate, resulting in the removal of a portion 140 of the process layer 130 disposed within the trench 120. This phenomenon is commonly referred to as dishing. It is also possible that portions 150 of the base layer 110 may be removed during the polishing process, resulting in a phenomenon commonly referred to as erosion. In general, the susceptibility of the process layer 130 to dishing and the base layer 110 to erosion is dependent somewhat on the width and spacing (i.e., pitch) of the trenches 120. Wider features allow the polishing pad to conform to the surface easier and exacerbate a dishing problem. Collectively, dishing and erosion are referred to herein as surface degradation.
Surface degradation can cause various problems in the fabrication of the semiconductor device 100. For example, dishing reduces the amount of the process layer 130 (e.g., silicon dioxide or conductive material) disposed in the trenches. If the amount of material removed is significant, the electrical properties of the features may be altered. For example, an STI structure may have reduced insulating capacity and a conductive feature may have increased resistivity. Likewise, erosion affects the properties of the base layer 110. Surface degradation can result in a reduction in the performance of the completed device (e.g., speed rating, power consumption, leakage current, etc.).
Hence, the process control goal of removing the process layer competes with the defect reduction goals of minimizing dishing or erosion and of not leaving remnants of process layer material behind.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
One aspect of the present invention is seen in a method including processing workpieces in accordance with an operating recipe. Metrology data associated with at least one of the workpieces is received. A proposed control action is generated based on the metrology data. A defectivity metric is generated based on the proposed control action. The proposed control action is modified based on the defectivity metric.
Another aspect of the present invention is seen in a manufacturing system including a process tool, a metrology tool, and a process controller. The process tool is configured to process workpieces in accordance with an operating recipe. The metrology tool is configured to provide metrology data associated with at least one of the workpieces. The process controller is configured to generate a proposed control action based on the metrology data, generate a defectivity metric based on the proposed control action, and modify the proposed control action based on the defectivity metric.